Non-volatile memory devices such as EEPROMs or similar devices may be capable of storing information even when the supply of external power is stopped. EPROMs may include an EPROM having a stacked-gate structure in which two polycrystalline silicon layers acting as a gate are vertically stacked, an EPROM having a single gate structure using a single polycrystalline silicon layer, and similar configurations.
Stacked-gate structure EPROMs may be advantageous for high integration of devices, but stacked-gate structure EPROMs may have the drawback of requiring a relatively complicated manufacturing process that includes manufacturing together with logic devices (e.g. metal oxide semiconductor field effect transistors (MOSFET) or complementary MOSFET (CMOSFET) that use a single gate process in a single-layered structure). However, single gate structure EPROMs have a relatively simple standard process, even though single gate structure EPROMs may have drawbacks compared to stacked-gate structure EPROMs in terms of cell integration and performance.
Accordingly, single gate structure EEPROMs may often be embedded in CMOS logic and mixed-signal circuits and usefully applied as low-priced, low-density devices. A single gate structure EPROM may be compatible with a standard logic process and therefore memory cell functions may be added without significant additional processes or cost. Accordingly, single gate structure EPROMs may be easily mounted in a logic device product.
FIG. 1 is a top plan view of an EPROM having a single gate structure and FIG. 2 is a cross-sectional view of the EPROM shown in FIG. 1, in accordance with the related art. An EPROM may include P-type well 12 and N-type well 13 formed in parallel on/over a semiconductor substrate 11. P-type well 12 and N-type well 13 may be isolated from each other by swallow trench isolation (STI) region 14. First gate insulation film 15 may be formed on/over semiconductor substrate 11 where P-type well 12 is formed. First gate 16 or a select gate (SG) may be formed on/over first gate insulation film 15.
An N-type source junction region may be formed in an upper portion of P-type well 12 at one side of first gate 16. An N-type drain junction region may be formed in an upper portion of P-type well 12 at the other side of first gate 16. Accordingly, select NMOS transistor 1 may be formed by first gate 16 and source/drain junction regions 18. Similarly, first gate insulation film 15 may be formed on/over semiconductor substrate 11 where N-type well 13 is formed. Second gate 17 or floating gate (FG) may be formed on/over first gate insulation film 15.
A P-type source junction region may be formed in an upper portion of N-type well 13 at one side of second gate 17. A P-type drain junction region may be formed in an upper portion of N-type well 13 at the other side of second gate 17. Floating PMOS transistor 2 may be formed by second gate 17 and source/drain junction regions 19. Salicide blocking layer 20 may be formed on/over second gate 17, thereby preventing salicide from being formed on second gate 17.
However, EPROMs according to the related art may have a problem that electrical erasure is impossible or unreliable even with the advantage of a simplified standard manufacturing process.